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3.3V CMOS 16-BIT LATCHED TRANSCEIVER
Integrated Device Technology, Inc.
IDT74FCT163543/A/C ADVANCE INFORMATION
FEATURES:
* 0.5 MICRON CMOS Technology * Typical tSK(o) (Output Skew) < 250ps * ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) * Packages include 25 mil pitch SSOP, 19.6 mil pitch TSSOP and 15.7 mil pitch TVSOP * Extended commercial range of -40C to +85C * VCC = 3.3V 0.3V, Normal Range or VCC = 2.7 to 3.6V, Extended Range * CMOS power levels (0.4W typ. static) * Rail-to-Rail output swing for increased noise margin * Low Ground Bounce (0.3V typ.) * Inputs (except I/O) can be driven by 3.3V or 5V components
DESCRIPTION:
The FCT163543/A/C 16-bit latched transceivers are built using advanced dual metal CMOS technology. These highspeed, low-power devices are organized as two independent 8bit D-type latched transceivers with separate input and output control to permit independent control of data flow in either direction. For example, the A-to-B Enable (xCEAB) must be LOW in order to enter data from the A port or to output data from the B port. xLEAB controls the latch function. When xLEAB is LOW, the latches are transparent. A subsequent LOW-toHIGH transition of xLEAB signal puts the A latches in the storage mode. xOEAB performs output enable function on the B port. Data flow from the B port to the A port is similar but requires using xCEBA, xLEBA, and xOEBA inputs. Flow-through organization of signal pins simplifies layout. All inputs are designed with hysteresis for improved noise margin. The FCT163543/A/C have series current limiting resistors. These offer low ground bounce, minimal undershoot, and controlled output fall times-reducing the need for external series terminating resistors.
FUNCTIONAL BLOCK DIAGRAM
1OEBA 1CEBA 1LEBA 1OEAB 1CEAB 1LEAB
2OEBA 2CEBA 2LEBA 2OEAB 2CEAB 2LEAB
C
1A1
2A1
C
1B1
D C D
D C D
2B1
TO 7 OTHER CHANNELS
3250 drw 01
TO 7 OTHER CHANNELS
3250 drw 02
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
(c)1996 Integrated Device Technology, Inc.
SEPTEMBER 1996
8.7
DSC-3250/2
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IDT74FCT163543/A/C 3.3V CMOS 16-BIT LATCHED TRANSCEIVER
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATIONS
PIN DESCRIPTION
Pin Names xOEAB xOEBA Description A-to-B Output Enable Input (Active LOW) B-to-A Output Enable Input (Active LOW) A-to-B Enable Input (Active LOW) B-to-A Enable Input (Active LOW) A-to-B Latch Enable Input (Active LOW) B-to-A Latch Enable Input (Active LOW) A-to-B Data Inputs or B-to-A 3-State Outputs B-to-A Data Inputs or A-to-B 3-State Outputs
3250 tbl 01
1OEAB 1LEAB 1CEAB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 SO56-1 43 SO56-2 SO56-3 42 41 40 39 38 37 36 35 34 33 32 31 30 29
1OEBA 1LEBA 1CEBA
xCEAB xCEBA xLEAB xLEBA xAx xBx
GND
1A1 1A2
GND
1B1 1B2
VCC
1A3 1A4 1A5
VCC
1B3 1B4 1B5
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM(2) VTERM(3) VTERM(4) TSTG IOUT Description Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Storage Temperature DC Output Current Max. -0.5 to +4.6 -0.5 to +7.0 -0.5 to VCC + 0.5 -65 to +150 -60 to +60 Unit V V V C mA
GND
1A6 1A7 1A8 2A1 2A2 2A3
GND
1B6 1B7 1B8 2B1 2B2 2B3
GND
2A4 2A5 2A6
GND
2B4 2B5 2B6
3250 lnk 03 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Vcc terminals. 3. Input terminals. 4. Output and I/O terminals.
VCC
2A7 2A8
VCC
2B7 2B8
FUNCTION TABLE(1, 3)
For A-to-B (Symmetric with B-to-A)
Inputs xCEAB CEAB H X L L L L xLEAB LEAB X H L H L H xOEAB OEAB X X L L H H Latch Status xAx to xBx Storing Storing Transparent Storing Transparent Storing Output Buffers xBx High Z X Current A Inputs Previous(2) A Inputs High Z High Z
GND
2CEAB 2LEAB 2OEAB
GND
2CEBA 2LEBA 2OEBA
SSOP/ TSSOP/TVSOP TOP VIEW
3250 drw 03
CAPACITANCE (TA = +25C, f = 1.0MHz)
Symbol CIN Input Capacitance CI/O I/O Capacitance Parameter(1) Conditions VIN = 0V VOUT = 0V Typ. 3.5 3.5 Max. Unit 6.0 pF 8.0 pF
3250 lnk 04
NOTES: 3250 tbl 02 1. A-to-B data flow shown; B-to-A flow control is the same, except using xCEBA, x LEBA and xOEBA. 2. Before xLEAB LOW-to-HIGH Transition 3. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care
NOTE: 1. This parameter is measured at characterization but not tested.
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IDT74FCT163543/A/C 3.3V CMOS 16-BIT LATCHED TRANSCEIVER
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Commercial: TA = -40C to +85C, VCC = 2.7V to 3.6V
Symbol VIH VIL II H II L IOZH IOZL VIK IODH IODL VOH Parameter Input HIGH Level (Input pins) Input HIGH Level (I/O pins) Input LOW Level (Input and I/O pins) Input HIGH Current (Input pins) Input HIGH Current (I/O pins) Input LOW Current (Input pins) Input LOW Current (I/O pins) High Impedance Output Current (3-State Output pins) Clamp Diode Voltage Output HIGH Current Output LOW Current Output HIGH Voltage VCC = Max. VCC = Max. VI = 5.5V VI = VCC VI = GND VI = GND VO = VCC VO = GND VCC = Min., IIN = -18mA VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V(3) VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V(3) VCC = Min. VIN = VIH or VIL VCC = 3.0V VIN = VIH or VIL VCC = Min. VIN = VIH or VIL IOH = -0.1mA IOH = -3mA IOH = -8mA IOL = 0.1mA IOL = 16mA IOL = 24mA VCC = 3.0V IOL = 24mA VIN = VIH or VIL VCC = Max., VO = GND(3)
--
Test Conditions(1) Guaranteed Logic HIGH Level Guaranteed Logic LOW Level
Min. 2.0 2.0 -0.5 -- -- -- -- -- -- -- -36 50 VCC-0.2 2.4 2.4 (5) -- -- -- -- -60 -- --
Typ.(2) -- --
--
Max. 5.5 VCC+0.5 0.8
Unit V V
-- -- -- -- -- -- -0.7
1 1 1 1 1 1
-1.2
A
A
V mA mA V
-60 90 -- 3.0 3.0 -- 0.2 0.3 0.3
-135
-110 200 -- -- -- 0.2 0.4 0.55 0.50 -240
--
VOL
Output LOW Voltage
V
IOS VH ICCL ICCH ICCZ
Short Circuit Current(4) Input Hysteresis Quiescent Power Supply Current
mA mV
150 0.1
VCC = Max., VIN = GND or VCC
10
A
NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 3.3V, +25C ambient. 3. Not more than one output should be tested at one time. Duration of the test should not exceed one second. 4. This parameter is guaranteed but not tested. 5. VOH = VCC -0.6V at rated current.
3250 lnk 05
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IDT74FCT163543/A/C 3.3V CMOS 16-BIT LATCHED TRANSCEIVER
COMMERCIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Symbol ICC ICCD Parameter Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current(4) Test Conditions(1) VCC = Max. VIN = VCC -0.6V(3) VCC = Max., Outputs Open xCEAB and xOEAB = GND xCEBA = VCC One Input Toggling 50% Duty Cycle VCC = Max., Outputs Open fi = 10MHz 50% Duty Cycle xLEAB, xCEAB and xOEAB= GND xCEBA = VCC One Bit Toggling VCC = Max., Outputs Open fi = 2.5MHz 50% Duty Cycle xLEAB, xCEAB and xOEAB= GND xCEBA = VCC Sixteen Bits Toggling VIN = VCC VIN = GND Min. -- -- Typ.(2) 2.0 60 Max. 30 100 Unit A A/ MHz
IC
Total Power Supply Current(6)
VIN = VCC VIN = GND
--
0.6
1.0
mA
VIN = VCC -0.6V VIN = GND
--
0.6
1.0
VIN = VCC VIN = GND
--
2.4
4.0(5)
VIN = VCC -0.6V VIN = GND
--
2.4
4.3(5)
NOTES: 1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 3.3V, +25C ambient. 3. Per TTL driven input; all other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (fCPNCP/2 + fiNi) ICC = Quiescent Current (ICCL, ICCH and ICCZ) ICC = Power Supply Current for a TTL High Input DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) NCP = Number of Clock Inputs at fCP fi = Input Frequency Ni = Number of Inputs at fi
3250 tbl 06
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IDT74FCT163543/A/C 3.3V CMOS 16-BIT LATCHED TRANSCEIVER
COMMERCIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE(4)
FCT163543 Symbol Parameter Condition(1) Min.(2) Max. FCT163543A Min.(2) Max. FCT163543C Min.(2) Max. Unit
Propagation Delay Transparent Mode xAx to xBx or xBx to xAx tPLH Propagation Delay tPHL xLEBA to xAx, xLEAB to xBx tPZH Output Enable Time tPZL xOEBA or xOEAB to xAx or xBx xCEBA or xCEAB to xAx or xBx tPHZ Output Disable Time tPLZ xOEBA or xOEAB to xAx or xBx xCEBA or xCEAB to xAx or xBx tSU Set-up Time HIGH or LOW xAx or xBx to xLEAB or xLEBA tH Hold Time HIGH or LOW xAx or xBx to xLEAB or xLEBA tW xLEBA or xLEAB Pulse Width LOW tSK(o) Output Skew (3)
tPLH tPHL
CL = 50pF RL = 500
1.5
8.5
1.5
6.5
1.5
5.3
ns
1.5 1.5
12.5 12.0
1.5 1.5
8.0 9.0
1.5 1.5
7.0 8.0
ns ns
1.5
9.0
1.5
7.5
1.5
6.5
ns
3.0 2.0 5.0 --
-- -- -- 0.5
2.0 2.0 5.0 --
-- -- -- 0.5
2.0 2.0 5.0 --
-- -- -- 0.5
ns ns ns ns
NOTES: 3250 tbl 07 1. See test circuits and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. 4. Propagation Delays and Enable/Disable times are with VCC = 3.3V 0.3V, Normal Range. For VCC = 2.7V to 3.6V, Extended Range, all Propagation Delays and Enable/Disable times should be degraded by 20%.
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IDT74FCT163543/A/C 3.3V CMOS 16-BIT LATCHED TRANSCEIVER
COMMERCIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS TEST CIRCUITS FOR ALL OUTPUTS
6V V
CC
SWITCH POSITION
Open GND
500 V Pulse Generator R
T IN
V D.U.T.
OUT
Test Open Drain Disable Low Enable Low Disable High Enable High All Other tests
Switch 6V
50pF C
L
500
3250 drw 05
SET-UP, HOLD AND RELEASE TIMES
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. tSU
tH
tREM
tSU
tH
PROPAGATION DELAY
3V 1.5V 0V VOH 1.5V VOL 3V 1.5V 0V
3250 drw 08
SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL
GND Open
DEFINITIONS: 3250 lnk 08 CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
PULSE WIDTH
3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V
3250 drw 06
LOW-HIGH-LOW PULSE tW HIGH-LOW-HIGH PULSE
1.5V
1.5V
3250 drw 07
ENABLE AND DISABLE TIMES
ENABLE CONTROL INPUT tPZL OUTPUT NORMALLY SWITCH 6V LOW tPZH OUTPUT NORMALLY HIGH SWITCH GND 3V 1.5V tPHZ 0.3V 1.5V 0V 0V
3250 drw 09
DISABLE 3V 1.5V tPLZ 0V 3V 0.3V VOL VOH
NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. 2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns. 3. If VCC is below 3V, input voltage swings should be adjusted not to exceed VCC.
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IDT74FCT163543/A/C 3.3V CMOS 16-BIT LATCHED TRANSCEIVER
COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT FCT XXXX X Device Temperature Type Range X Package
PV PA PF
Shrink Small Outline Package (SO56-1) Thin Shrink Small Outline Package (SO56-2) Thin Very Small Outline Package (SO56-3)
163543 16-Bit Latched Transceiver 163543A 163543C 74 -40C to +85C
3250 drw 10
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